PIC18F4539-E/PT【PDF 33/322 页】IC PIC MCU FLASH 12KX16 44TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3879

29页 30页 31页 32页 [33页]34页 35页 36页 37页

PIC18FXX39

DS30485A-page 126

Preliminary

2002 Microchip Technology Inc.

16.3.1

REGISTERS

The MSSP module has four registers for SPI mode

operation. These are:

MSSP Control Register1 (SSPCON1)

MSSP Status Register (SSPSTAT)

Serial Receive/Transmit Buffer (SSPBUF)

MSSP Shift Register (SSPSR) - Not directly

accessible

SSPCON1 and SSPSTAT are the control and status

registers in SPI mode operation. The SSPCON1 regis-

ter is readable and writable. The lower 6 bits of the

SSPSTAT are read only. The upper two bits of the

SSPSTAT are read/write.

SSPSR is the shift register used for shifting data in or

out. SSPBUF is the buffer register to which data bytes

are written to or read from.

In receive operations, SSPSR and SSPBUF together

create a double-buffered receiver. When SSPSR

receives a complete byte, it is transferred to SSPBUF

and the SSPIF interrupt is set.

During

transmission,

the

SSPBUF

not

double-buffered. A write to SSPBUF will write to both

SSPBUF and SSPSR.

REGISTER 16-1:

SSPSTAT: MSSP STATUS REGISTER (SPI MODE)

R/W-0

R-0

SMP

CKE

D/A

R/W

bit 7

bit 0

bit 7

SMP: Sample bit

SPI Master mode:

= Input data sampled at end of data output time

= Input data sampled at middle of data output time

SPI Slave mode:

SMP must be cleared when SPI is used in Slave mode

bit 6

CKE: SPI Clock Edge Select bit

When CKP = 0:

= Data transmitted on rising edge of SCK

= Data transmitted on falling edge of SCK

When CKP = 1:

= Data transmitted on falling edge of SCK

= Data transmitted on rising edge of SCK

bit 5

D/A: Data/Address bit

Used in I2C mode only

bit 4

P: STOP bit

Used in I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is

cleared.

bit 3

S: START bit

Used in I2C mode only

bit 2

R/W: Read/Write bit information

Used in I2C mode only

bit 1

UA: Update Address

Used in I2C mode only

bit 0

BF: Buffer Full Status bit (Receive mode only)

= Receive complete, SSPBUF is full

= Receive not complete, SSPBUF is empty

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式